Resistive memory arrays are widely used in integrated circuits. A typical memory cell in a resistive memory array includes resistive devices having at least two states, a high-resistance state and a low-resistance state. The state of a memory cell may be determined by applying a voltage to the memory cell, and determining the current flowing through the memory cell.
FIG. 1 illustrates a portion of a conventional resistive memory array, which includes a plurality of resistive cells arranged in rows and columns. Taking memory cell 2, which is in row j−1 and column i−1, as an example, memory cell 2 includes selection transistor 4 and resistive cell 6, wherein selection transistor 4 is connected to word-line WLj−1, and resistive cell 6 is connected to bit-line BLi−1. Selection transistor 4 controls the selection of resistive cell 6.
In the recent study of resistive memory arrays, phase change memory (PCM) appears to be a promising candidate for the next-generation non-volatile memories. The operation of PCM memory cells is based on the electrically induced phase change of chalcogenide material, typically Ge2Sb2Te5 (GST). The two cell logic states, namely reset and set states, correspond to high and low resistances of the amorphous and the crystalline phases of the active chalcogenide material, respectively. The transitions between two states, which include amorphization and crystallization, are achieved by Joule heating in the chalcogenide material. The amorphization is obtained through melting and rapidly cooling the chalcogenide material, while the crystallization is obtained by holding the chalcogenide material at a high temperature, which is below the melting temperature of the chalcogenide material, for a period of time.
Typically, resistive memory cells need high programming currents. Particularly, the chalcogenide materials need high currents to generate enough Joule heat. Conventionally, bipolar junction transistors (BJT) were favored over metal-oxide-semiconductor (MOS) devices for their ability of providing higher drive currents. However, BJTs are less process-friendly than MOS devices, and their manufacturing involves higher production cost. On the other hand, MOS devices require more chip area than BJTs to provide the same currents as BJTs. Designers thus have to compromise between production cost and chip area usage. Accordingly, new structures and manufacturing methods are needed to manufacture selection transistors that provide enough current for operating resistive cells, while at the same time consuming less chip area.